View ICS870S208_8617995.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICS870S208bklf revision a april 3, 2013 1 ?2013 integrated device technology, inc. datasheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch ICS870S208 general description the ICS870S208 is a low skew, eight output lvcmos / lvttl fanout buffer with selectable divider. the ICS870S208 has two selectable inputs that accept a variet y of differential input types. the device provides the capability to s uppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. the low impedance lvcmos outputs are designed to drive 50 ?? series or parallel terminated transmission lines. the effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated lines. the divide select inputs, div_sela and div_selb, control the output frequency of each bank. the output banks can be independently selected for 1 or 2 operation. the output enable pins assigned to each output, support enabling an d disabling of each output individually. the ICS870S208 is characterized at full 3.3v and 2.5v, and mixed 3.3v/2.5v output oper ating supply modes. guaranteed output and part-to-part skew characteristics make the ICS870S208 ideal for high performance, single ended applications. features ? eight lvcmos/lvttl outputs, (2 banks of 4 outputs) each output has individual synchronous output enable ? two selectable differential clkx, nclkx inputs ? dual differential input pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl ? maximum output frequency: 250mhz ? selectable ? 1 or ? 2 operation ? glitchless output behavio r during input switch ? output skew: 120ps (maximum), 3.3v ? bank skew: 65ps (maximum), 3.3v ? supply modes: core/output 3.3v/3.3v 2.5v/2.5v 3.3v/2.5v ? 0c to 70c ambient operating temperature ? lead-free (rohs 6) packaging block diagram pin assignment ICS870S208 32-lead vfqfn 5mm x 5mm x 0.9mm package body 3.15mm x 3.15mm epad size k package top view 1 2 0 1 0 1 0 1 pulldown pulldown pulldown pulldown pullup pullup pulldown qa0 div_sela clk0 nclk0 clk1 clk_sel nclk1 div_selb oe_a0 qa1 oe_a1 qa2 oe_a2 qa3 oe_a3 qb0 oe_b0 qb1 oe_b1 qb2 oe_b2 qb3 oe_b3 9 10 11 12 13 14 15 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 div_selb clk0 nclk0 v dd clk_sel clk1 nclk1 div_sela oe_b3 oe_b2 oe_b1 oe_b0 oe_a3 oe_a2 oe_a1 oe_a0 gnd qa0 qa1 v ddoa v ddob qb0 qb1 gnd qa2 qa3 v ddoa v ddob qb2 qb3 gnd gnd 16
ICS870S208bklf revision a april 3, 2013 2 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch pin descriptions an d characteristics table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1 div_selb input pulldown controls frequency division for bank b outputs. lvcmos / lvttl interface levels. 2 clk0 input pulldown non-inverting differential clock input. 3 nclk0 input pullup inverting differential clock input. 4v dd power power supply pin. 5 clk_sel input pulldown clock select input. when high, selects cl k1, nclk1 inputs, when low, selects clk0, nclk0 inputs. lvcmos / lvttl interface levels. 6 clk1 input pulldown non-inverting differential clock input. 7 nclk1 input pullup inverting differential clock input. 8 div_sela input pulldown controls frequency division for bank a outputs. lvcmos / lvttl interface levels. 9, 16, 25, 32 gnd power power supply ground. 10, 11, 30, 31 qa0, qa1, qa3, qa2 output single-ended bank a clock outputs. lvcmos / lvttl interface levels. 12, 29 v ddoa power output supply pins for bank a outputs. 13, 28 v ddob power output supply pins for bank b outputs. 14, 15 26, 27 qb0, qb1, qb3, qb2 output single-ended bank b clock outputs. lvcmos / lvttl interface levels. 17 oe_a0 input pullup output enable for qa0 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 18 oe_a1 input pullup output enable for qa1 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 19 oe_a2 input pullup output enable for qa2 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 20 oe_a3 input pullup output enable for qa3 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 21 oe_b0 input pullup output enable for qb0 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 22 oe_b1 input pullup output enable for qb1 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 23 oe_b2 input pullup output enable for qb2 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels. 24 oe_b3 input pullup output enable for qb3 output. active high. if oe pin is low, outputs will drive in high-impedance. see table 3. lv cmos / lvttl interface levels.
ICS870S208bklf revision a april 3, 2013 3 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch table 2. pin characteristics function tables table 3. output enable function table note: where x = a or b. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf c pd power dissipation capacitance (per output) v dd = v ddoa, b = 3.465v 8 pf v dd = v ddoa, b = 2.625v 7 pf v dd = 3.465v, v ddoa, b = 2.625v 7 pf r pullup input pullup resistor 50 k ? r pulldown input pulldown resistor 50 k ? r out output impedance 15 ? control inputs outputs oe_x [0:3] qa[0:3], qb[0:3] 0 high-impedance 1 (default) active
ICS870S208bklf revision a april 3, 2013 4 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch function description two valid clocks the ics87s0208 has a glitch free i nput mux that is controlled by the clk_sel pin. it is designed to switch between 2 input clocks whether running or not. in the case where bot h clocks are running, when clk_sel changes, the output clocks go low after one cycle of the output clock (nominally). the outputs then stay low for one cycle of the new input clock (nominally) and then begin to follow the new input clock. this is shown in figure 1a. figure 1a. clk_sel timing diagram when div_sel changes, the part waits for the output to complete the cycle of the selected divider then changes seamlessly to the new divider. figure 1b. div_selx timing diagram when an output enable pin is pulled low, the part waits for the output to complete its period, then transi tions to an high-impedance state. when output enable is asserted, the output transitions from a high-impedance to a low state to ensure a clean rising edge of the first output clock. figure 1c. oex timing diagram clk0 clk1 clk_sel output clk 1 clk 2 div_sel output clk1 oe output
ICS870S208bklf revision a april 3, 2013 5 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch bad input clock an internal timer monitors the stat e of both input clocks. if a clock is stopped (stuck high or low for over approximately 200ns), its internal input bad flag is set and the part will perform as depicted in the following diagrams. if the clock is restored, the internal input bad detector waits for 4 full clock periods before clearing the input bad flag and returning to normal operation. if the selected input clock goes bad (stuck high or low for over approximately 200ns), an internal input bad flag is set. when the input bad flag is set, the output goes low until the next valid clock event. if the selected clock is restored, the input bad detector waits 4 full clock periods before clearing the flag and returning to normal operation. if clk_sel is changed to select a valid input clock, the output will stay low for one full period of the new input clock, then return to normal operation. figure 1d. clk_sel with bad input timing diagram if the selected input clock goes bad (stuck high or low for over approximately 200ns), an internal input bad flag is set. when the input bad flag is set, the output goes low until the next valid clock event. if div_sel is changed, t he output will transition from the low state following the selected divide when a valid input clock is restored. figure 1e. div_selx with bad input timing diagram if the input bad flag has been set (the input has been stuck high or low for over approximately 200ns), a nd oex is pulled low, the output will immediately go to a high-impedance state. if the clock is restored while the oex is low, the output will transition from the high- impedance to a low state to ensure a clean rising edge of the first output clock when the oex is pulled high again. figure 1f. oex with bad input timing diagram clk0 clk1 clk_sel output input bad detect, 200ns clk2 div_sel output input bad detect, 200ns clk clk oe output input bad detect, 200ns
ICS870S208bklf revision a april 3, 2013 6 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch switch during an input bad detect if a clk_sel, div_sel, or oe event happens after a clock has stopped, but before the input b ad flag has been set (during the ~200ns detect period) the output change will not take effect until the internal bad flag has been set. the output will go low after the input bad flag is set and follow the second period of the new clock input. although no glitches will occur, due to the unknown state of the failing clock, a transition may take up to 1us to execute. figure 1g. clk_sel with bad input timing diagram clk0 clk1 clk_sel output input bad detect, 200ns
ICS870S208bklf revision a april 3, 2013 7 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to th e device. these ratings are stress specifications only. functional operat ion of product at these co nditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating co nditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddoa = v ddob = 3.3v 5%, t a = 0c to 70c table 4b. power supply dc characteristics, v dd = v ddoa = v ddob = 2.5v 5%, t a = 0c to 70c table 4c. power supply dc characteristics, v dd = 3.3v 5%, v ddoa = v ddob = 2.5v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddoa, b + 0.5v package thermal impedance, ? ja 42.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddoa, v ddob output supply voltage 3.135 3.3 3.465 v i dd power supply current 80 ma i ddoa, i ddob output supply current no load 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddoa, v ddob output supply voltage 2.375 2.5 2.625 v i dd power supply current 80 ma i ddoa, i ddob output supply current no load 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddoa, v ddob output supply voltage 2.375 2.5 2.625 v i dd power supply current 80 ma i ddoa, i ddob output supply current no load 1 ma
ICS870S208bklf revision a april 3, 2013 8 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch table 4d. lvcmos/lvttl dc characteristics, t a = 0c to 70c note 1: outputs are terminated with 50 ? to v ddoa, b /2. see parameter measurement section, load test circuit diagrams. table 4e. differential dc characteristics, v dd = 3.3v 5% or 2.5v 5%, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.3v 5% 2.2 v dd + 0.3 v v dd = 2.5v 5% 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v 5% -0.3 0.8 v v dd = 2.5v 5% -0.3 0.7 v i ih input high current clk_sel, div_sela, div_selb v dd = v in = 3.465v or 2.625v 150 a oe_a[0:3], oe_b[0:3] v dd = v in = 3.465v or 2.625v 10 a i il input low current clk_sel, div_sela, div_selb v dd = 3.465v or 2.625v, v in = 0v -10 a oe_a[0:3], oe_b[0:3] v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddoa, vddob = 3.465v 2.6 v v ddoa, vddob = 2.625v 1.8 v v ol output low voltage; note 1 v ddoa, vddob = 3.465v or 2.625v 0.55 v symbol parameter test conditio ns minimum typical maximum units i ih input high current nclk0, nclk1 v dd = v in = 3.465v or 2.625v 10 a clk0, clk1 v dd = v in = 3.465v or 2.625v 150 a i il input low current nclk0, nclk1 v dd = 3.465v or 2.625v, v in = 0v -150 a clk0, clk1 v dd = 3.465v or 2.625v, v in = 0v -10 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ICS870S208bklf revision a april 3, 2013 9 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch ac electrical characteristics table 5a. ac characteristics, v dd = v ddoa = v ddob = 3.3v 5% = t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature range, which is established when th e device is mounted in a test socket with maintained tr ansverse airflow greater than 500 lfpm. t he device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crosspoint to v ddoa, b /2 of the output. note 2: defined as between outputs at the same supply voltage and with equal load conditions. measured at v ddoa, b /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of input on each device, the output is measured at v ddoa, b /2. note 5: defined as skew within a bank of outputs at the same voltage and with equal load conditions. note 6: these parameters are guaranteed by characterization. not tested in production. table 5b. ac characteristics, v dd = v ddoa = v ddob = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature range, which is established when th e device is mounted in a test socket with maintained tr ansverse airflow greater than 500 lfpm. t he device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crosspoint to v ddoa, b /2 of the output. note 2: defined as between outputs at the same supply voltage and with equal load conditions. measured at v ddoa, b /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of input on each device, the output is measured at v ddoa, b /2. note 5: defined as skew within a bank of outputs at the same voltage and with equal load conditions. note 6: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f out output frequency 250 mhz t pd propagation delay; note 1 2.3 3.8 ns t sk(o) output skew; note 2, 3 120 ps t sk(pp) part-to-part skew; note 3, 4 225 ps t sk(b) bank skew; note 3, 5 qa[0:3], nqa[0:3] 65 ps qb[0:3], nqb[0:3] 60 ps t r / t f output rise/fall time 20% to 80% 150 600 ps t en output enable time; note 6 10 ns t dis output disable time; note 6 10 ns odc output duty cycle 45 55 % symbol parameter test conditio ns minimum typical maximum units f out output frequency 250 mhz t pd propagation delay; note 1 2.4 4.0 ns t sk(o) output skew; note 2, 3 135 ps t sk(pp) part-to-part skew; note 3, 4 225 ps t sk(b) bank skew; note 3, 5 qa[0:3], nqa[0:3] 70 ps qb[0:3], nqb[0:3] 60 ps t r / t f output rise/fall time 20% to 80% 150 600 ps t en output enable time; note 6 10 ns t dis output disable time; note 6 10 ns odc output duty cycle 44 56 %
ICS870S208bklf revision a april 3, 2013 10 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch table 5c. ac characteristics, v dd = 3.3v 5%, v ddoa = v ddob = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature range, which is established when th e device is mounted in a test socket with maintained tr ansverse airflow greater than 500 lfpm. t he device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crosspoint to v ddoa, b /2 of the output. note 2: defined as between outputs at the same supply voltage and with equal load conditions. measured at v ddoa, b /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of input on each device, the output is measured at v ddoa, b /2. note 5: defined as skew within a bank of outputs at the same voltage and with equal load conditions. note 6: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f out output frequency 250 mhz t pd propagation delay; note 1 2.5 4.1 ns t sk(o) output skew; note 2, 3 140 ps t sk(pp) part-to-part skew; note 3, 4 225 ps t sk(b) bank skew; note 3, 5 qa[0:3], nqa[0:3] 70 ps qb[0:3], nqb[0:3] 60 ps t r / t f output rise/fall time 20% to 80% 150 600 ps t en output enable time; note 6 10 ns t dis output disable time; note 6 10 ns odc output duty cycle 40 60 %
ICS870S208bklf revision a april 3, 2013 11 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch parameter measureme nt information 3.3v output load test circuit 3.3v core/2.5v output load test circuit output skew 2.5v output load test circuit differential input level part-to-part skew scope qx gnd v dd, 1.65v5% -1.65v5% v ddoa, v ddob scope qx lvcmos v ddo 2 gnd 2.05v5% -1.25v5% v dd 1.25v5% v ddoa, v ddob t sk(o) v dd 2 v dd 2 qx qy scope qx gnd 1.25v5% -1.25v5% v dd, v ddoa, v ddob nclk[0:1] clk[0:1] v dd gnd v cmr cross points v pp t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy
ICS870S208bklf revision a april 3, 2013 12 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch parameter measure ment information, continued bank skew output duty cycle/pulse width/period propagation delay output rise/fall time t sk(b) v ddox 2 v ddox 2 qxx qxy where x denotes bank a or bank b outputs t period t pw t period odc = v ddo 2 x 100% t pw qa[0:3], qb[0:3] t pd v ddo 2 clk0, clk1 qa[0:3], qb[0:3] nclk0, nclk1 20% 80% 80% 20% t r t f qa[0:3], qb[0:3]
ICS870S208bklf revision a april 3, 2013 13 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch applications information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be in creased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels
ICS870S208bklf revision a april 3, 2013 14 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch differential clock input interface the clkx /nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl differential in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
ICS870S208bklf revision a april 3, 2013 15 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch vfqfn epad thermal release path in order to maximize both the remo val of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb pr ovides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is in corporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recomm endations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ICS870S208bklf revision a april 3, 2013 16 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch power considerations this section provides information on power dissipa tion and junction temperature for the ICS870S208. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS870S208 is the sum of the co re power plus the analog power plus the power dissipated due to into the load. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * i dd = 3.465v *80ma = 277.2mw ? output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 15 ? )] = 26.7ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 15 ? * (26.7ma) 2 = 10.69mw per output ? total power (r out ) = 10.69mw * 8 = 85.52mw dynamic power dissipation at 250mhz power (250mhz) = c pd * frequency * (v dd ) 2 = 8pf * 250mhz * (3.465v) 2 = 24mw per output total power (250mhz) = 24mw * 8 = 192mw total power dissipation ? total power = power (core) max + power (r out ) + power (250mhz) = 277.2mw + 85.52mw + 192mw = 554.72mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 42.7c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.555w *42.7c/w = 93.7c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w
ICS870S208bklf revision a april 3, 2013 17 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch reliability information table 7. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ICS870S208 is: 2788 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w
ICS870S208bklf revision a april 3, 2013 18 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 8. package dimensions reference document: jedec publication 95, mo-220 note: the package mechanical dra wing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin c ount or pin layout of this device. the pin count and pin-out are show n on the front page. the package dimensions are in table 8. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ing u l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 method s of indic a ting pin 1 corner a t the ba ck of the vfqfn p a ck a ge: 1. type a: ch a mfer on the p a ddle (ne a r pin 1) 2. type c: mo us e b ite on the p a ddle (ne a r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ICS870S208bklf revision a april 3, 2013 19 ?2013 integrated device technology, inc. ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch ordering information table 9. ordering information part/order number marking package shipping packaging temperature 870s208bklf ICS870S208bl ?lead-free? 32 lead vfqfn tray 0 ? c to 70 ? c 870s208bklft ICS870S208bl ?lead-free? 32 lead vfqfn tape & reel 0 ? c to 70 ? c
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the d escribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty o f mer- chantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involv ing extreme environmental conditio ns or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the hea lth or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement b y idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contact idt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution ICS870S208 data sheet differential-to-lvcmos/lvttl fanout buffer w/divider and glitchless switch

▲Up To Search▲

Price & Availability of ICS870S208

	To Download ICS870S208 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .